| US 7,464,357 B2 | ||
| Integrated circuit capable of locating failure process layers | ||
| An-Ru Andrew Cheng, Hsin-Chu (Taiwan); Chang-Song Lin, Hsinchu (Taiwan); Tzu-Chun Liu, Taipei (Taiwan); and Huan-Yung Tseng, Hsinchu (Taiwan) | ||
| Assigned to Faraday Technology Corp., Hsin-Chu (Taiwan) | ||
| Filed on Jan. 30, 2006, as Appl. No. 11/341,481. | ||
| Application 11/341481 is a continuation of application No. 10/626634, filed on Jul. 25, 2003, granted, now 7,036,099. | ||
| Prior Publication US 2006/0123375 A1, Jun. 08, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—11 [716/1; 716/14] | 13 Claims |
| 1. An integrated circuit on a chip, comprising:
a substrate; and
a scan chain disposed in the substrate, with scan cells connected to form a series chain, each connection being formed according
to a layout constraint with a minimum dimension provided by design rules for an assigned routing layer, such that the series
chain is vulnerable to variations in processing that are relevant to an assigned routing process.
|