| US 7,464,254 B2 | ||
| Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data | ||
| Harshvardhan Sharangpani, Santa Clara, Calif. (US); Manoj Khare, Saratoga, Calif. (US); Kent Fielden, Sunnyvale, Calif. (US); Rajesh Patil, Santa Clara, Calif. (US); and Judge Kennedy Arora, Los Gatos, Calif. (US) | ||
| Assigned to Cisco Technology, Inc., San Jose, Calif. (US) | ||
| Filed on Jan. 08, 2004, as Appl. No. 10/755,188. | ||
| Claims priority of provisional application 60/438847, filed on Jan. 09, 2003. | ||
| Prior Publication US 2004/0215593 A1, Oct. 28, 2004 | ||
| Int. Cl. G06F 7/00 (2006.01) | ||
| U.S. Cl. 712—300 [712/220] | 25 Claims |
| 1. A programmable rule processor comprising:
a general purpose register file;
an instruction sequencer to provide instructions;
a decoder coupled to the general purpose register file and instruction sequencer to decode a set of instructions specified
by the instruction sequencer; and
a state machine unit coupled to the decoder and the general purpose register file and having a plurality of state machine
register sets to store the states of a plurality of state machines and a plurality of state machine execution hardware units
coupled to the plurality of state machine register sets to evaluate the plurality of state machines in parallel, wherein each
state machine register set is coupled to a state machine execution hardware unit, so that each state machine unit could respond
in parallel to executing one or more of the decoded set of instructions and on independent information from one or both of
the decoder and the general purpose register file.
|