US 7,464,115 B2
Node synchronization for multi-processor computer systems
John Carter, Salt Lake City, Utah (US); Randal S. Passint, Chippewa Falls, Wis. (US); Donglai Dai, Eau Claire, Wis. (US); Zhen Fang, Salt Lake City, Utah (US); Lixin Zhang, Austin, Tex. (US); and Gregory M. Thorson, Altoona, Wis. (US)
Assigned to Silicon Graphics, Inc., Sunnyvale, Calif. (US)
Filed on Apr. 25, 2005, as Appl. No. 11/113,805.
Prior Publication US 2006/0242308 A1, Oct. 26, 2006
Int. Cl. G06F 13/42 (2006.01)
U.S. Cl. 707—201  [711/147; 711/154; 711/141; 365/189.08] 27 Claims
OG exemplary drawing
 
1. A method of controlling access by a set of accessing nodes to shared memory of a home node, the home node and accessing nodes being part of a multi-node shared-memory computer system, the method comprising:
determining that each node in the set of nodes has accessed the shared memory; and
forwarding a completion message to each node in the set of nodes after it is determined that each node has accessed the shared memory, the completion message having data indicating that each node in the set of nodes has accessed the shared memory of the home node.