| US 7,463,546 B2 | ||
| Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders | ||
| Luca G. Fasoli, San Jose, Calif. (US); Christopher J. Petti, Mountain View, Calif. (US); and Roy E. Scheuerlein, Cupertino, Calif. (US) | ||
| Assigned to SanDisk 3D LLC, Milpitas, Calif. (US) | ||
| Filed on Jul. 31, 2006, as Appl. No. 11/461,364. | ||
| Prior Publication US 2008/0025132 A1, Jan. 31, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.06 [365/230.05; 365/163; 365/154; 365/174; 365/148] | 25 Claims |
| 1. A method for operating an integrated circuit memory array, said memory array comprising a cross-point array of passive
element memory cells, each coupled between an associated word line and an associated bit line, said method comprising:
in a first mode of operation, biasing selected word lines at a lower voltage than unselected word lines, and biasing selected
bit lines at a higher voltage than unselected bit lines; and
in a second mode of operation, biasing selected word lines at a higher voltage than unselected word lines, and biasing selected
bit lines at a lower voltage than unselected bit lines.
|