| US 7,463,536 B2 | ||
| Memory array incorporating two data busses for memory array block selection | ||
| Roy E. Scheuerlein, Cupertino, Calif. (US); Luca G. Fasoli, San Jose, Calif. (US); and Christopher J. Petti, Mountain View, Calif. (US) | ||
| Assigned to SanDisk 3D LLC, Milpitas, Calif. (US) | ||
| Filed on Jul. 31, 2006, as Appl. No. 11/461,359. | ||
| Prior Publication US 2008/0025085 A1, Jan. 31, 2008 | ||
| Int. Cl. G11C 8/12 (2006.01) | ||
| U.S. Cl. 365—189.18 [365/230.06; 365/230.04; 365/230.03; 365/163; 365/148] | 30 Claims |
| 1. An integrated circuit comprising:
a memory array including a first plurality of array blocks, each array block comprising a plurality of word lines and bit
lines;
a first data bus generally spanning the first plurality of array blocks, each of a first group of the first plurality of array
blocks associated with the first data bus;
a second data bus generally spanning the first plurality of array blocks, each of a second group of the first plurality of
array blocks associated with the second data bus;
a row selection circuit configured, in a first mode of operation, to simultaneously select a word line in a first array block
within the first group and a word line in a second array block within the second group; and
a column selection circuit configured, in the first mode of operation, to simultaneously couple one or more selected bit lines
in the first array block to corresponding lines of the first data bus and one or more selected bit lines in the second array
block to corresponding lines of the second data bus.
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