| US 7,463,102 B2 | ||
| Clock synthesizer with clock divider outside feedback loop and method thereof | ||
| Cheng-Yen Huang, Hsin-Chu (Taiwan) | ||
| Assigned to Faraday Technology Corp., Hsin-Chu (Taiwan) | ||
| Filed on Oct. 04, 2006, as Appl. No. 11/538,804. | ||
| Prior Publication US 2008/0094146 A1, Apr. 24, 2008 | ||
| Int. Cl. H03B 1/00 (2006.01) | ||
| U.S. Cl. 331—74 [331/25; 327/156; 375/376] | 23 Claims |
| 1. A clock synthesizer comprising:
a phase locked loop (PLL) having a reference end and a clock-out end;
a clock divider having an input end coupled to the clock-out end of the PLL, an output end, and a control end;
a phase comparator having a first input end coupled to the output end of the clock divider, a second input end coupled to
the clock-out end of the PLL, a third input end coupled to the reference end of the PLL, and a transmission end coupled to
the control end of the clock divider; and
a first buffer coupled between the output end of the clock divider and the first input end of the phase comparator.
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