| US 7,613,973 B2 | ||
| Method for providing bitwise constraints for test generation | ||
| Vitaly Lagoon, Caulfield South (Australia); and Guy Baruch, Natania (Israel) | ||
| Assigned to Cadence Design (Israel) II Ltd., Rosh Ha'Ayin (Israel) | ||
| Filed on Dec. 20, 2004, as Appl. No. 11/15,020. | ||
| Application 11/015020 is a continuation of application No. 09/939743, filed on Aug. 28, 2001, granted, now 6,918,076. | ||
| Claims priority of provisional application 60/228087, filed on Aug. 28, 2000. | ||
| Prior Publication US 2005/0203720 A1, Sep. 15, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 11/263 (2006.01); G06F 11/16 (2006.01) | ||
| U.S. Cl. 714—738 [714/735] | 13 Claims |
| 1. A method stored on a computer readable medium for providing a bitwise constraint for computer based test generation for
design verification via device simulation, the method comprising:
encoding a processing device according to a language structure for expressing the bitwise constraint, said language structure
including at least one constraint parameter and at least one operator, said constraint parameter being further constrained
to an interval containing at least one value, said interval having interval limits;
actuating the processing device to propagate information bi-directionally to determine interval limits for said constraint
parameters at least partially according to the bitwise constraint; and
actuating the processing device to compute one or more permissible values for the constraint parameter, thereby to resolve
arithmetic and bitwise constraints together.
|