| US 7,613,969 B2 | ||
| Method and system for clock skew independent scan register chains | ||
| Sandeep Bhatia, San Jose, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Mar. 16, 2005, as Appl. No. 11/81,315. | ||
| Claims priority of provisional application 60/623464, filed on Oct. 29, 2004. | ||
| Prior Publication US 2006/0095819 A1, May 04, 2006 | ||
| Int. Cl. G01R 31/28 (2006.01); H03K 3/289 (2006.01) | ||
| U.S. Cl. 714—729 [714/726; 714/731; 327/202] | 14 Claims |
| 1. A method, comprising:
operating a tester to assert a scan-enable signal;
asserting the scan enable signal to an inactive value during a scan data capture cycle, wherein the inactive value is equivalent
to a logic low;
pulsing a clock signal during the capture cycle;
asserting the scan enable signal to an active value during a shift scan cycle, wherein the active value is equivalent to a
logic high;
locking scan data into a first master latch of a negative-edge triggered scan register having the first master latch and a
first slave latch when the clock signal has a falling edge;
asserting the scan enable signal to the inactive value;
transferring the scan data from the first master latch to the first slave latch to compensate for clock skew;
asserting the scan enable signal to the active value;
locking the scan data into a second master latch of a positive-edge triggered scan register having the second master latch
and a second slave latch when the clock signal has a rising edge; and
asserting the scan enable signal to the inactive value; and
transferring the scan data from the second master latch to the second slave latch to compensate for clock skew.
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