	US 7,613,901 B2
	Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation
Donald E. Alfano, Round Rock, Tex. (US); Danny J. Allred, Austin, Tex. (US); Douglas S. Piasecki, Austin, Tex. (US); Kenneth W. Fernald, Austin, Tex. (US); Ka Y. Leung, Austin, Tex. (US); Brian Caloway, Georgetown, Tex. (US); Alvin Storvik, Austin, Tex. (US); Paul Highley, Austin, Tex. (US); and Douglas R. Holberg, Wimberley, Tex. (US)
Assigned to Silicon Labs CP, Inc., Austin, Tex. (US)
Filed on Mar. 30, 2007, as Appl. No. 11/694,629.
Application 11/694629 is a continuation of application No. 11/618644, filed on Dec. 29, 2006, granted, now 7,498,962.
Application 11/618644 is a continuation of application No. 09/885459, filed on Jun. 19, 2001, granted, now 7,171,542, filed on Jan. 30, 2007.
Claims priority of provisional application 60/212653, filed on Jun. 19, 2000.
Prior Publication US 2007/0296478 A1, Dec. 27, 2007
Int. Cl. G06F 19/00 (2006.01); H03K 5/22 (2006.01)

U.S. Cl. 712—37 [327/68; 327/78]

11 Claims

1. An integrated circuit package on a single chip, comprising:

a processing core for operating on a set of instructions to carry out predefined processes;

a plurality of comparators for performing compare operations within the integrated circuit package;

at least one control register associated with each of the plurality of comparators for storing a first group of control bits controlling an amount of positive hysteresis of each of the plurality of comparators and a second group of control bits controlling an amount of negative hysteresis of each of the plurality of comparators;

wherein each of the plurality of comparators are software programmable to control a hysteresis of the plurality of comparators responsive to control bits established in the at least one control register by the processing core, the amount of positive hysteresis programmed via the first group of the control bits in the at least one control register and the amount of negative hysteresis programmed via the second group of the control bits in the at least one control register;

a crossbar switch for assigning an output of the plurality of comparators to package pins; and

wherein when a comparator output is assigned to the package pins, the comparator output can be programmed by the processing core to operate in either an open drain mode or a push-pull mode.