| US 7,613,265 B2 | ||
| Systems, methods and computer program products for high speed data transfer using an external clock signal | ||
| John E. Campbell, Wappingers Falls, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Sep. 05, 2006, as Appl. No. 11/470,067. | ||
| Prior Publication US 2008/0059831 A1, Mar. 06, 2008 | ||
| Int. Cl. H04L 7/02 (2006.01); H03D 3/24 (2006.01) | ||
| U.S. Cl. 375—360 [375/376] | 29 Claims |
| 20. A buffer device in a memory system, the buffer device comprising:
an external clock port for receiving an external clock signal having a first frequency, a first edge, and a second edge, wherein
a clock period of the external clock is the amount of time between any two successive first edges;
a first plurality of signal link ports for receiving parallel data at a second frequency faster than the first frequency;
and
logic in communication with the external clock port and the first plurality of signal link ports for facilitating:
transforming the external clock signal into an internal clock signal based on the first edge and not the second edge of the
external clock signal, wherein the internal clock signal consists of any one of a first internal clock signal running at the
second frequency, a plurality of second internal clock signals running at the first frequency wherein each second internal
clock signal comprises a pulse such that the combination of clock pulses of the plurality of second internal clock signals
constitute said second frequency, or a plurality of clock signals running at the second frequency; and
capturing the parallel data using the internal clock signal.
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