US 7,611,989 B2
Polysilicon dummy wafers and process used therewith
James E. Boyle, Saratoga, Calif. (US); Reese Reynolds, Los Gatos, Calif. (US); Raanan Y. Zehavi, Sunnyvale, Calif. (US); Robert W. Mytton, Salem, Oreg. (US); Doris Mytton, legal representative; and Tom L. Cadwell, Los Altos, Calif. (US)
Assigned to Integrated Materials, Inc., Sunnyvale, Calif. (US)
Filed on Dec. 18, 2007, as Appl. No. 11/959,354.
Application 11/959354 is a continuation in part of application No. 11/328438, filed on Jan. 09, 2006.
Claims priority of provisional application 60/871618, filed on Dec. 22, 2006.
Claims priority of provisional application 60/658075, filed on Mar. 03, 2005.
Claims priority of provisional application 60/694334, filed on Jun. 27, 2005.
Prior Publication US 2008/0152805 A1, Jun. 26, 2008
Int. Cl. H01L 21/44 (2006.01)
U.S. Cl. 438—680  [438/657; 438/753; 257/E21.17; 257/E21.054; 257/E21.227; 257/E21.237; 257/E21.278; 257/E21.293; 257/E21.483] 14 Claims
OG exemplary drawing
 
1. A nitride deposition process having a cycle of deposition, comprising
disposing monocrystalline silicon production wafers on some slots of a support tower,
disposing at least one polycrystalline non-production wafer on other slots of the support tower,
in a furnace in which the support tower is disposed, depositing silicon nitride on the production and non-production wafers by chemical vapor deposition; and
repeating the cycle of deposition with different production wafers and the same non-production wafer;
wherein the repeating step continues until silicon nitride is deposited on the same non-production wafer to a thickness of at least 1 micron.