| US 7,611,979 B2 | ||
| Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks | ||
| Alessandro C. Callegari, Yorktown Heights, N.Y. (US); Michael P. Chudzik, Danbury, Conn. (US); Barry P. Linder, Hastings-on-Hudson, N.Y. (US); Renee T. Mo, Briarcliff Manor, N.Y. (US); Vijay Narayanan, New York, N.Y. (US); Dae-Gyu Park, Poughquag, N.Y. (US); Vamsi K. Paruchuri, New York, N.Y. (US); and Sufi Zafar, Briarcliff Manor, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Feb. 12, 2007, as Appl. No. 11/673,901. | ||
| Prior Publication US 2008/0191292 A1, Aug. 14, 2008 | ||
| Int. Cl. H01L 21/3205 (2006.01); H01L 21/28 (2006.01) | ||
| U.S. Cl. 438—588 [438/586; 438/605; 257/E21.621; 257/E21.639] | 6 Claims |
| 1. A method of forming a multilayered gate stack comprising:
forming a metal nitrogen-containing layer composed of a metal and nitrogen on a surface of a high-k gate dielectric, said
metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1, and said metal is selected
from Group IVB, VB, VIB and VIIB of the Periodic Table of Elements; and
a forming a Si-containing conductor located directly on a surface of said metal nitrogen-containing layer.
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