| US 7,611,933 B2 | ||
| Process for manufacturing a thin-film transistor (TFT) device and TFT device manufactured by the process | ||
| Salvatore Leonardi, Aci Sant'Antonio (Italy); and Claudia Caligiore, Giarre (Italy) | ||
| Assigned to STMicroelectronics, S.r.l., Agrate Brianza (Italy) | ||
| Filed on Jun. 28, 2006, as Appl. No. 11/478,332. | ||
| Claims priority of application No. 05425477 (EP), filed on Jul. 05, 2005. | ||
| Prior Publication US 2007/0034872 A1, Feb. 15, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 21/84 (2006.01) | ||
| U.S. Cl. 438—166 [438/149; 438/592; 257/E21.205; 257/E21.094] | 25 Claims |
| 1. A process for manufacturing a thin-film transistor device comprising:
forming a dielectric insulation layer on a substrate;
forming an amorphous silicon layer on said dielectric insulation layer;
crystallizing said amorphous silicon layer so as to obtain polycrystalline silicon;
forming gate structures on said polycrystalline silicon; and
forming first doped regions within said polycrystalline silicon laterally with respect to said gate structures;
wherein crystallizing comprises:
forming first capping dielectric regions on said amorphous silicon layer; and
after forming first capping dielectric regions, irradiating said amorphous silicon layer using a laser, so as to form active
areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying said first capping dielectric
regions, wherein the horizontal dimension of at least one of said active areas differs from the horizontal dimension of another
of said active areas, and wherein the horizontal dimension of each active area is selected to obtain desired electrical properties
for that active area.
|