| US 7,606,974 B2 | ||
| Automatic caching generation in network applications | ||
| Jinquan Dai, Shanghai (China); Luddy Harrison, Chestnut, Mass. (US); Long Li, Shanghai (China); and Bo Huang, Shanghai (China) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Appl. No. 10/589,398 PCT Filed May 26, 2004, PCT No. PCT/CN2004/000538 § 371(c)(1), (2), (4) Date Aug. 14, 2006, PCT Pub. No. WO2005/116837, PCT Pub. Date Dec. 08, 2005. |
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| Prior Publication US 2007/0198772 A1, Aug. 23, 2007 | ||
| Int. Cl. G06F 12/02 (2006.01) | ||
| U.S. Cl. 711—118 [711/128; 711/155; 712/220; 712/225] | 21 Claims |
| 1. A computer-implemented method, comprising:
identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external
memory accesses, the one or more external memory accesses having an identical base address, including
partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based
on dependency relationships of the instructions,
converting addresses of each external memory accesses into a form having a base address and an offset,
grouping multiple potential candidates having the identical base address into a single candidate, wherein a group having most
of the potential candidates is selected as a final candidate for caching, and
selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency
relationship; and
inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate
to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify
at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform
the respective external memory access.
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