| US 7,605,477 B2 | ||
| Stacked integrated circuit assembly | ||
| Tse E. Wong, Los Alamitos, Calif. (US); Samuel D. Tonomura, Rancho Palos Verdes, Calif. (US); Stephen E. Sox, La Canada, Calif. (US); Timothy E. Dearden, Torrance, Calif. (US); Clifton Quan, Arcadia, Calif. (US); Polwin C. Chan, Monterey Park, Calif. (US); and Mark S. Hauhe, Hermosa Beach, Calif. (US) | ||
| Assigned to Raytheon Company, Waltham, Mass. (US) | ||
| Filed on Jan. 25, 2007, as Appl. No. 11/698,602. | ||
| Prior Publication US 2008/0179758 A1, Jul. 31, 2008 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01) | ||
| U.S. Cl. 257—777 [257/778; 257/686; 257/E23.021] | 16 Claims |
| 1. A stacked integrated circuit assembly, comprising:
a substrate having a top surface with at least one substrate connection pad;
a first flip chip integrated circuit (FFIC) disposed above the substrate;
a second flip chip integrated circuit (SFIC) disposed above the FFIC, the FFIC disposed between the substrate and the SFIC;
a first solder connection between the substrate connection pad and the FFIC; and
a second solder connection between the FFIC and the SFIC,
wherein a first melting temperature of the first solder connection is different than a second melting temperature of the second
solder connection and wherein connection pads of the FFIC, the SFIC and the substrate are coplanar with respective surfaces
of the FFIC, the SFIC and the substrate, the respective surfaces each face corresponding solder connections.
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