a plurality of memory arrays each having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells;

an input/output buffer section for inputting and outputting data from/to outside;

a multiplexer section for said input/output buffer section, and

a plurality of sense amplifier arrays each disposed to correspond to one of said plurality of memory arrays and each of which includes a plurality of sense amplifiers, a local I/O line, and a plurality of read/write ports coupled between the plurality of bit lines and the local I/O line, each sense amplifier being connected to a respective pair of the bit lines of the corresponding memory array,

wherein at least one corresponding error correction code circuit of a plurality of error correction code circuits is disposed near each said sense amplifier array, each error correction code circuit performing an error correction when an error is present in a part of data read to sense amplifiers of the corresponding sense amplifier array,

wherein at least one of the plurality of read/write ports is activated to transfer data, which has been error-corrected by at least one of the error correction code circuits and is held in the plurality of sense amplifiers, to the local I/O line,

wherein said plurality of memory arrays include a plurality of normal memory arrays and a redundant memory array providing a redundant bit for a redundant replacement,

wherein said redundant replacement is performed by substituting any one of said plurality of normal memory arrays with said redundant memory array,

wherein when said redundant replacement substituting a first memory array of said plurality of normal memory arrays with said redundant memory array is performed, information is read out from memory cells of said redundant memory array instead of from memory cells of said first memory array, and

wherein said memory array substitution in said redundant replacement is performed when said multiplexer section selects a connection between said input/output buffer section and said redundant memory array.