| US 7,603,497 B2 | ||
| Method and apparatus to launch write queue read data in a microprocessor recovery unit | ||
| Michael J. Mack, Round Rock, Tex. (US); and Kenneth L. Ward, Austin, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jan. 27, 2009, as Appl. No. 12/360,116. | ||
| Application 12/360116 is a continuation of application No. 11/165484, filed on Jun. 23, 2005, granted, now 7,526,583. | ||
| Prior Publication US 2009/0132854 A1, May 21, 2009 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 3/00 (2006.01); G06F 5/00 (2006.01) | ||
| U.S. Cl. 710—54 [714/724] | 12 Claims |
| 1. A queue circuit for a recovery unit, comprising:
a register having N number of entries with N corresponding outputs;
a first signal path for a current read value corresponding to a current read entry of said register, said first signal path
including a first N-to-1 multiplexer having inputs respectively connected to said outputs of said register, wherein the current
read entry is output from said first N-to-1 multiplexer responsive to a first select signal pointing to a current read position;
a second signal path for a next read value corresponding to a next read entry of said register, said second signal path including
a second N-to-1 multiplexer which is separate from said first N-to-1 multiplexer, having inputs respectively connected to
said outputs of said register, wherein the next read entry is output from said second N-to-1 multiplexer responsive to a second
select signal pointing to a next read position;
a capture latch; and
a 2-to-1 output multiplexer separate from said first and second N-to-1 multiplexers which receives inputs from the first signal
path and the second signal path in parallel and selectively passes one of the current read value and next read value to said
capture latch based on an instruction completion signal.
|