| US 7,603,398 B2 | ||
| Data converter and a delay threshold comparator | ||
| Atul Maheshwari, Portland, Oreg. (US); Sanu K. Matthew, Hillsboro, Oreg. (US); Mark A. Anders, Hillsboro, Oreg. (US); and Ram Krishnamurthy, Portland, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Mar. 31, 2005, as Appl. No. 11/94,811. | ||
| Prior Publication US 2006/0221724 A1, Oct. 05, 2006 | ||
| Int. Cl. G06F 7/00 (2006.01); G06F 15/00 (2006.01) | ||
| U.S. Cl. 708—210 [708/203] | 30 Claims |
| 15. A circuit, comprising:
a converter to convert 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value, the converter
including:
N comparators to generate respective bit values in the N-bit value,
each comparator to determine whether the number of bits in the data having the predetermined logical value exceeds a respective
one of a plurality of reference values, wherein a first one of the reference values equals a predetermined value and remaining
ones of the reference values are based on the bit values output from one or more preceding ones of the N comparators, wherein
each comparator is a delay threshold comparator including:
a first delay element to delay a signal by a first amount based on a number of bits in a data value having a predetermined
logical value;
a second delay element to delay the signal by a second amount different from the first amount based on a number of bits in
a reference value having the predetermined logical value; and
a comparator to generate a bit value based on a difference in delay between the delayed signals output from the first delay
element and the second delay element.
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