| US 7,602,644 B2 | ||
| Memory devices with page buffer having dual registers and method of using the same | ||
| June Lee, Seoul (Korea, Republic of); Oh-Suk Kwon, Taegu Kwang Yuk (Korea, Republic of); and Heung-Soo Im, Kyung Ki Do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Apr. 11, 2007, as Appl. No. 11/734,102. | ||
| Application 11/734102 is a continuation of application No. 11/284604, filed on Nov. 21, 2005, granted, now 7,227,785. | ||
| Application 11/284604 is a continuation of application No. 11/153638, filed on Jun. 14, 2005, granted, now 6,996,014, filed on Feb. 07, 2006. | ||
| Application 11/153638 is a continuation of application No. 10/315897, filed on Dec. 09, 2002, granted, now 7,042,770, filed on May 09, 2006. | ||
| Application 10/315897 is a continuation in part of application No. 10/013191, filed on Dec. 07, 2001, granted, now 6,671,204, filed on Dec. 30, 2003. | ||
| Claims priority of provisional application 60/307572, filed on Jul. 23, 2001. | ||
| Prior Publication US 2007/0189079 A1, Aug. 16, 2007 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.12 [365/189.05] | 12 Claims |
| 1. A read method for a nonvolatile memory device which includes a page buffer having a first register and a second register,
comprising:
initializing the second register after discharging a bit line;
precharging the bit line with a bit line voltage;
isolating the bit line from the second register; and
connecting the second register and the bit line to latch data in a selected memory cell connected to the bit line.
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