| US 7,602,386 B2 | ||
| Reference clock signal generation circuit, power supply circuit, driver circuit, and electro-optical device | ||
| Kazuhiro Maekawa, Chino (Japan) | ||
| Assigned to Seiko Epson Corporation, Tokyo (Japan) | ||
| Filed on May 18, 2006, as Appl. No. 11/436,035. | ||
| Claims priority of application No. 2005-159516 (JP), filed on May 31, 2005. | ||
| Prior Publication US 2006/0267901 A1, Nov. 30, 2006 | ||
| Int. Cl. G09F 3/08 (2006.01); G09G 5/00 (2006.01); H03L 3/00 (2006.01); H03K 21/00 (2006.01); H03K 25/00 (2006.01); H03L 7/00 (2006.01) | ||
| U.S. Cl. 345—204 [345/211; 345/212; 345/213; 327/115; 327/116; 327/119; 327/148; 327/152; 327/291] | 12 Claims |
| 1. A reference clock signal generation circuit for generating a reference clock signal for a charge-pump operation which raises
or lowers a voltage, the reference clock signal generation circuit comprising:
a clock signal generation circuit which generates a reference clock signal having one of first to nth (n is an integer of
two or more) frequencies;
a wait time setting register in which a value corresponding to a wait time is set; and
a frequency setting register in which a value corresponding to one of the first to nth frequencies is set;
the clock signal generation circuit generating the reference clock signal having a predetermined frequency in a start period
from start of the charge-pump operation to completion of the wait time, and generating the reference clock signal having a
frequency corresponding to the value set in the frequency setting register in an operation period after the start period.
|