| US 7,602,018 B2 | ||
| High withstand-voltage semiconductor device | ||
| Takeshi Iida, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kawasaki, Kanagawa (Japan) | ||
| Filed on May 03, 2004, as Appl. No. 10/836,275. | ||
| Claims priority of application No. 2003-131017 (JP), filed on May 09, 2003. | ||
| Prior Publication US 2005/0051840 A1, Mar. 10, 2005 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—339 [257/342; 257/343; 257/500] | 21 Claims |
| 1. A high withstand-voltage semiconductor device including an MOS transistor, comprising:
a semiconductor layer of one conductivity type;
a gate electrode of said MOS transistor which is formed on said semiconductor layer;
a source diffusion layer and a drain diffusion layer of an opposite conductivity type to that of said semiconductor layer
which are formed at a surface of said semiconductor layer;
a gate insulating layer of said MOS transistor having a portion between said drain diffusion layer and said gate electrode
which has a thickness greater than a thickness of another portion of said gate insulating layer;
an offset diffusion layer of said opposite conductivity type which is in direct contact with said drain diffusion layer other
than a top surface of said drain diffusion layer and which includes a low impurity concentration; and
a buried layer of said one conductivity type including a portion that lies directly under the gate electrode being longer
than another portion of the buried layer that does not lie directly under the gate electrode,
the buried layer formed in said semiconductor layer at a depth substantially equal to a depth of said offset diffusion layer
and includes a greater impurity concentration than that of said semiconductor layer.
|