| US 7,602,016 B2 | ||
| Semiconductor apparatus and method of manufacturing the same | ||
| Nobuaki Yasutake, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 11, 2007, as Appl. No. 11/808,490. | ||
| Application 11/808490 is a division of application No. 11/044630, filed on Jan. 28, 2005, granted, now 7,244,988. | ||
| Claims priority of application No. 2004-022912 (JP), filed on Jan. 30, 2004. | ||
| Prior Publication US 2007/0241397 A1, Oct. 18, 2007 | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—331 [257/336; 257/410; 438/574] | 20 Claims |
| 1. A semiconductor apparatus comprising:
a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film provided therebetween;
a three-layered gate sidewall insulating structure comprising a first nitride film, an oxide film, and a second nitride film,
wherein the three-layered structure is formed on a sidewall of an upper portion of the gate electrode;
a two-layered gate sidewall insulating structure comprising the oxide film and the second nitride film, wherein the two-layered
structure is formed on a sidewall of a lower portion of the gate electrode; and
a raised source/drain region comprising an impurity region formed in a surface layer of the semiconductor substrate,
wherein the gate electrode comprises:
a polysilicon germanium layer;
a polysilicon layer; and
a silicide layers,
wherein the polysilicon germanium layer, the polysilicon layer, and the silicide layer are sequentially formed on the semiconductor
substrate in the order,
wherein a width of the lower portion of the gate electrode is larger than that of the upper portion of the gate electrode,
and
wherein the three-layered structure is formed on a sidewall of the silicide layer and a sidewall of the polysilicon layer.
wherein the two-layered structure is formed on a sidewall of the polysilicon germanium layer.
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