| US 7,601,638 B2 | ||
| Interconnect metallization method having thermally treated copper plate film with reduced micro-voids | ||
| Masahiko Hasunuma, Yokohama (Japan); Hisashi Kaneko, Fujisawa (Japan); and Hiroshi Toyoda, Kamakura (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 29, 2007, as Appl. No. 11/926,614. | ||
| Claims priority of application No. P2006-293488 (JP), filed on Oct. 30, 2006. | ||
| Prior Publication US 2008/0102628 A1, May 01, 2008 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—660 [257/E21.495] | 10 Claims |
| 1. A method for manufacturing a semiconductor device, comprising:
preparing a substrate having a recessed portion on a surface;
forming a plating film to bury the recessed portion, the plating film having a lower portion and an upper portion, including
a higher impurity concentration in the upper portion than in the lower portion, and a boundary of the lower portion and the
upper portion being at a height 1.2 times as large as or larger than a depth of the recessed portion from a bottom surface
of the recessed portion;
thermally treating the plating film; and
removing the thermally treated plating film except for a portion buried in the recessed portion.
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