| US 7,601,623 B2 | ||
| Method of manufacturing a semiconductor device with a gate electrode having a laminate structure | ||
| Yoshinori Tsuchiya, Yokohama (Japan); and Masato Koyama, Kanagawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 16, 2008, as Appl. No. 12/219,096. | ||
| Application 12/219096 is a continuation of application No. 11/329228, filed on Jan. 11, 2006, granted, now 7,429,777. | ||
| Claims priority of application No. P2005-051355 (JP), filed on Feb. 25, 2005. | ||
| Prior Publication US 2008/0280405 A1, Nov. 13, 2008 | ||
| Int. Cl. H01L 21/28 (2006.01); H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—592 [438/597; 438/675; 257/E21.204; 257/E21.424] | 9 Claims |
| 1. A method for manufacturing a semiconductor device, comprising:
forming an element separation insulating film layer in a semiconductor substrate so as to define a semiconductor layer on
the semiconductor substrate;
forming a gate electrode including:
a gate insulating film formed on the semiconductor layer,
a metal or a metallic compound formed on the gate insulating film,
a polycrystalline silicon layer formed on the metal or the metallic compound, and
a metal silicide formed on the polycrystalline silicon layer;
forming a source region and a drain region in the semiconductor layer so as to sandwich the gate electrode therebetween; and
forming a plug that passes through the metal silicide and the polycrystalline silicon layer and that contacts with the metal
or the metallic compound of the gate electrode.
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