US 7,599,229 B2
Methods and structures for expanding a memory operation window and reducing a second bit effect
Chao-I Wu, Zhubei (Taiwan)
Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan)
Filed on Jun. 21, 2006, as Appl. No. 11/425,482.
Prior Publication US 2007/0297240 A1, Dec. 27, 2007
Int. Cl. G11C 11/34 (2006.01)
U.S. Cl. 365—185.3  [365/230.06] 7 Claims
OG exemplary drawing
 
1. A method for programming a multi-bit memory cell having a charge trapping structure disposed between a gate and a substrate, and having a right bit charge storage site and a left bit charge storage site, the method comprising:
setting both of the right bit charge storage site and the left bit charge storage site of the multi-bit memory cell to a negative threshold voltage; and
after said setting, programming said one of the right bit and the left bit to a positive threshold voltage by a programming operation, said programming operation maintaining another of the right bit and the left bit to a negative threshold voltage.