an imaging region having a plurality of X-address lines and a plurality of Y-address lines formed thereon, a plurality of pixels being formed near the intersections of the X-address lines and the Y-address lines, each pixel having an independent address, wherein the imaging region provides each pixel with a reading address;

a first Y-register and a second Y-register to select an arbitrary line out of said plurality of Y-address lines;

a first X-register and a second X-register to select an arbitrary line out of said plurality of X-address lines;

a sequencer which provides the X- and Y address data for specifying each pixel corresponding regions that correspond to the configuration positions of the plural parts on the substrate within the imaging region;

a first switch that supplies output address data from the sequencer to the first Y-register or the second Y-register;

a second switch that supplies output address data from the first Y-register or the second Y-register to a plurality of the plurality of Y-address lines;

a third switch that supplies output address data from the sequencer to the first X-register or the second X-register;

a fourth switch that supplies output address data from the first X-register or the second X-register to a plurality of the plurality of X-address lines;

an address processor which transfers the address data to the sequencer; and

a memory unit including at least a first memory section having stored therein address data for specifying each pixel in regions corresponding to first plural parts, and a second memory section having stored therein address data for specifying each pixel in regions corresponding to second plural parts, as the address data to be given to the address processor, so that a plurality of substrates, having different configurations of the plural parts mounted thereon, can be inspected.