a plurality of dynamic logic circuits each having a clock input for controlling evaluation and pre-charging of a summing node and a plurality of logic inputs for determining whether or not to said evaluation in response to said clock changes a logical state of said summing node; and

a local clock buffer having a clock output connected to said clock input of each of said plurality of dynamic logic circuits, and wherein said local clock buffer includes a reduced-swing clock generator circuit having an output connected for generating a reduced-swing clock signal having an evaluate phase voltage state substantially differing from a voltage of a first power supply rail of said plurality of dynamic circuits and a pre-charge voltage state substantially equal to a voltage of a second power supply rail of said plurality of dynamic circuits.