	US 7,594,105 B2
	Multilayer print circuit board
Tohru Ohsaka, Yokohama (Japan)
Assigned to Canon Kabushiki Kaisha, Tokyo (Japan)
Filed on Dec. 05, 2006, as Appl. No. 11/566,942.
Claims priority of application No. 2005-358161 (JP), filed on Dec. 12, 2005.
Prior Publication US 2007/0136618 A1, Jun. 14, 2007
Int. Cl. H05K 7/08 (2006.01); H01P 5/02 (2006.01)

U.S. Cl. 713—2 [333/32; 333/33; 333/17.3; 333/263; 361/765; 361/780; 361/782; 29/825; 29/830; 29/852]

9 Claims

1. A multilayer print circuit board in which a semiconductor integrated circuit is mounted on a first surface layer and a bypass capacitor is mounted on a second surface layer on a side opposite to said first surface layer, and which has a power supply conductive layer and a ground conductive layer therein, comprising:

a first power supply via hole which connects to a power supply terminal of said semiconductor integrated circuit on said first surface layer and extends from said first surface layer to said second surface layer;

a power supply wiring which connects to said first power supply via hole on said second surface layer;

a ground via hole which connects to said ground conductive layer, extends from said ground conductive layer to said second surface layer, and connects to said power supply wiring on said second surface layer through said bypass capacitor;

a first clearance hole which is formed around a portion of said power supply conductive layer where said first power supply via hole extends, to eliminate any conductor so said first power supply via hole and said power supply conductive layer do not come into contact with each other; and

a second clearance hole which is formed around a portion of said ground conductive layer where said first power supply via hole extends, to eliminate any conductor so said first power supply via hole and said ground conductive layer do not come into contact with each other,

wherein said first clearance hole has a larger size than that of said second clearance hole.