| US 7,592,690 B2 | ||
| Semiconductor device including semiconductor elements mounted on base plate | ||
| Shinji Ohuchi, Tokyo (Japan); Shigeru Yamada, Tokyo (Japan); and Yasushi Shiraishi, Tokyo (Japan) | ||
| Assigned to Oki Semiconductor Co., Ltd., Tokyo (Japan) | ||
| Filed on Mar. 11, 2005, as Appl. No. 11/77,145. | ||
| Application 11/077145 is a division of application No. 10/657139, filed on Sep. 09, 2003. | ||
| Application 10/657139 is a division of application No. 09/757663, filed on Jan. 11, 2001, granted, now 6,673,651. | ||
| Application 09/757663 is a division of application No. 09/460984, filed on Dec. 15, 1999, granted, now 6,201,266. | ||
| Claims priority of application No. 11-187658 (JP), filed on Jul. 01, 1999. | ||
| Prior Publication US 2005/0156298 A1, Jul. 21, 2005 | ||
| Int. Cl. H01L 23/02 (2006.01) | ||
| U.S. Cl. 257—686 [257/777; 257/790; 257/E25.006; 257/23.085] | 8 Claims |
| 1. A semiconductor device comprising:
a base plate having main and back surfaces;
a first semiconductor element located above the main surface of the base plate;
a plurality of bumps formed on the back surface of the base plate;
a first sealing resin formed on the main surface of the base plate and on the first semiconductor element, to seal the first
semiconductor element; and
a second semiconductor element located on and to oppose a portion of the back surface of the base plate which does not have
the plurality of bumps formed thereon,
wherein the second semiconductor element has main and back surfaces, side surfaces between the main and back surfaces of the
second semiconductor element, and a plurality of terminals which are formed on the main surface of the second semiconductor
element and in contact with the base plate,
wherein the back surface and an entirety of the side surfaces of the second semiconductor element are exposed,
wherein all of the bumps are located on portions of the back surface of the base plate that are not below the first semiconductor
element,
wherein the main surface of the second semiconductor element is sealed with a second sealing resin so as to expose a part
of each of the terminals,
wherein a distance from a top surface of the first semiconductor element to a top surface of the first sealing resin is greater
than a distance from the main surface of the base plate to the top surface of the first semiconductor element, and
wherein the second semiconductor element is a chip size package disposed so that a gap without resin exists between the base
plate and the chip size package.
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