| US 7,592,216 B2 | ||
| Fabrication process of a semiconductor device having a capacitor | ||
| Jun Lin, Kawasaki (Japan); Hiroyuki Ogawa, Kawasaki (Japan); and Hideyuki Kojima, Kawasaki (Japan) | ||
| Assigned to Fujitsu Microelectronics Limited, Tokyo (Japan) | ||
| Filed on May 27, 2008, as Appl. No. 12/127,067. | ||
| Claims priority of application No. 2007-265838 (JP), filed on Oct. 11, 2007. | ||
| Prior Publication US 2009/0098696 A1, Apr. 16, 2009 | ||
| Int. Cl. H01L 21/8234 (2006.01) | ||
| U.S. Cl. 438—238 [438/243; 438/296; 438/385; 438/386] | 15 Claims |
| 1. A method of manufacturing a semiconductor device, comprising:
forming a first trench in a capacitor device region of a semiconductor substrate;
forming a capacitor insulation film over a sidewall surface of said first trench;
forming a semiconductor film to cover said first trench, a resistor device region of said semiconductor substrate and a logic
device region of said semiconductor substrate;
introducing a first impurity element into said semiconductor film formed over said first trench;
patterning said semiconductor film to form a top electrode in said capacitor device region, a resistor in said resistor device
region and a gate electrode in said logic device region;
annealing said semiconductor substrate; and
introducing a second impurity element in said resistor.
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