| US 7,587,577 B2 | ||
| Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content | ||
| Marc E. Royer, Garland, Tex. (US); Bharath M. Siravara, Issaquah, Wash. (US); Steven C. Bartling, Plano, Tex. (US); Charles M. Branch, Dallas, Tex. (US); Pedro R. Galabert, Allen, Tex. (US); Neeraj Mogotra, Richardson, Tex. (US); and Samil D. Kamath, Richardson, Tex. (US) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Nov. 08, 2006, as Appl. No. 11/557,755. | ||
| Claims priority of provisional application 60/736436, filed on Nov. 14, 2005. | ||
| Prior Publication US 2007/0113048 A1, May 17, 2007 | ||
| Int. Cl. G06F 13/00 (2006.01) | ||
| U.S. Cl. 712—34 [711/147; 712/225] | 14 Claims |
| 1. A co-processor subsystem comprising:
a co-processor having Fast Fourier Transform (FFT) circuitry and digital filter circuitry;
a bus slave circuit; and
a memory switch including:
a plurality of memory blocks;
switch circuitry having a plurality of transmission terminals and a plurality of selection terminals, wherein the FFT circuitry
is coupled to at least one of the transmission terminals, and wherein the digital filter circuitry is coupled to at least
one of the transmission terminals, and wherein the bus slave circuit is coupled to at least one of transmission terminals,
and wherein each memory block is coupled to at least one of the transmission terminals, and wherein the switch circuitry is
adapted to couple at least one of the functional units to at least one of the memory blocks, and wherein the switch circuitry
is adapted to coupled the bus slave circuit to at least one of the memory blocks;
a control register; and
control logic that is coupled to the control register and the selection terminals, wherein the control logic that controls
the switch circuitry based at least in part on the contents of the control register.
|