| US 7,586,139 B2 | ||
| Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor | ||
| James W. Adkisson, Jericho, Vt. (US); Jeffrey P. Gambino, Westford, Vt. (US); Mark D. Jaffe, Shelburne, Vt. (US); Alan Loiseau, Williston, Vt. (US); and Richard J. Rassel, Colchester, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Feb. 17, 2006, as Appl. No. 11/276,218. | ||
| Prior Publication US 2006/0102973 A1, May 18, 2006 Prior Publication US 2007/0194397 A1, Aug. 23, 2007 |
||
| Int. Cl. H01L 31/062 (2006.01); H01L 21/00 (2006.01) | ||
| U.S. Cl. 257—292 [257/290; 257/291; 257/447; 257/460; 257/E31.055; 438/48] | 20 Claims |

| 20. An imaging sensor cell comprising:
a semiconductor layer of a first conduction type;
a dielectric layer, wherein said semiconductor layer is an active silicon layer and said dielectric layer is an oxide layer;
an isolation trench to said dielectric layer surrounding said semiconductor layer;
an isolation well of a second conduction type in one surface of said semiconductor layer, said second conduction type being
opposite said first conduction type with said isolation well forming a photo-sensor on said one surface with said semiconductor
layer, the other surface of said semiconductor layer being at and adjacent to said dielectric layer, wherein said active silicon
layer is doped with an N-type dopant and said isolation well is a P-well in said N-type active silicon layer forming a photodiode,
said imaging sensor cell further comprising a plurality of NFETs formed in said P-well, said NFETs connected to selectively
sense an optical signal to said photodiode, wherein said plurality of NFETs comprises:
a first NFET connected between the cathode of said photodiode and a supply voltage (Vdd), said first NFET being gated by a reset signal,
a second NFET connected at the drain to said supply voltage and gated by said cathode, and
a third NFET connected between the source of said second NFET and a data output, said third NFET being gated by a pixel select
signal, wherein said active silicon layer and said oxide layer are silicon on insulator (SOI) layers in a CMOS SOI chip;
a color filter separated from said semiconductor layer by said dielectric layer; and
a protective layer on said color filter, light passing through said protective layer, through said dielectric layer and then,
through said semiconductor layer, and filtered by said color filter causing current flow across said semiconductor layer and
said isolation well junction being selectively sensed by said photo-sensor.
|