| US 7,577,056 B2 | ||
| System and method for using a DLL for signal timing control in a eDRAM | ||
| Kuoyuan Hsu, San Jose, Calif. (US) | ||
| Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Apr. 14, 2007, as Appl. No. 11/735,455. | ||
| Prior Publication US 2008/0252352 A1, Oct. 16, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—233 [365/194; 365/191] | 17 Claims |
| 1. An embedded dynamic random access memory (eDRAM) comprising:
a clock signal;
at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control
signals each having a predetermined delay from the clock signal;
a receive activate circuit coupled between the clock signal and the DLL circuit for controlling activations of the DLL circuit
when needed by a system; and
at least one DRAM array coupled to the plurality of control signals,
wherein the DRAM array operates in a plurality of steps controlled by the plurality of control signals.
|