| US 7,576,579 B2 | ||
| DLL circuit and semiconductor device including the same | ||
| Hiroki Fujisawa, Tokyo (Japan); and Ryuji Takishita, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Aug. 23, 2007, as Appl. No. 11/892,525. | ||
| Claims priority of application No. 2006-234921 (JP), filed on Aug. 31, 2006. | ||
| Prior Publication US 2008/0054959 A1, Mar. 06, 2008 | ||
| Int. Cl. H03L 7/06 (2006.01) | ||
| U.S. Cl. 327—158 [327/149; 327/161; 327/245; 327/271; 365/233.12; 365/233.13] | 7 Claims |
| 1. A DLL circuit comprising:
a dividing circuit unit that frequency-divides a first clock signal to generate at least first and second frequency-divided
signals having different phases;
a first delay adjusting circuit that adjusts an amount of delay of the first frequency-divided signal based on a first feedback
signal;
a second delay adjusting circuit that adjusts an amount of delay of the second frequency-divided signal based on a second
feedback signal;
a synthesizing circuit that synthesizes at least outputs of the first and second delay adjusting circuits to generate a second
clock signal, and supplies the second clock signal to a real path in a clock tree unit;
a first clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path
in the clock tree unit; and
a second clock driver that receives the output of the second delay adjusting circuit, wherein
the first clock driver and the second clock driver have substantially the same circuit configuration.
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