| US 7,576,423 B2 | ||
| Semiconductor device | ||
| Kazutaka Takagi, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 12, 2008, as Appl. No. 12/137,620. | ||
| Application 12/137620 is a division of application No. 11/317024, filed on Dec. 27, 2005, granted, now 7,411,288. | ||
| Claims priority of application No. 2004-381897 (JP), filed on Dec. 28, 2004. | ||
| Prior Publication US 2008/0246140 A1, Oct. 09, 2008 | ||
| Int. Cl. H01L 23/48 (2006.01) | ||
| U.S. Cl. 257—699 [257/E23.184] | 6 Claims |
| 1. A semiconductor device comprising:
a metallic base plate;
a semiconductor element arranged on the base plate,
at least a first dielectric plate, arranged on the base plate, having a surface on which a circuit pattern is formed;
a frame-shaped sidewall, provided on the base plate, surrounding the dielectric plate and the semiconductor element;
a power supply portion including insulator forming a part of the sidewall;
a band-shaped conductor provided at a higher position than the surface of the first dielectric plate with respect to a main
surface of the base plate, wherein the conductor penetrates through the power supply portion; and
a relay post provided on the dielectric plate;
wherein the relay post includes: an insulator block, at a center portion of which a VIA hole is formed in a vertical direction;
a VIA metal filled in the VIA hole, one end of which is connected to the circuit pattern and another end of which is extended
to a higher position than the surface of the dielectric plate; and a conductor layer, provided on a surface of the insulator
block, surrounding the VIA metal, and
wherein the first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.
|