| US 7,576,406 B2 | ||
| Semiconductor device | ||
| Yoichi Tamaki, Kokubunji (Japan); Hideaki Nonami, Ome (Japan); and Masato Hamamoto, Iruma (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Feb. 09, 2004, as Appl. No. 10/773,658. | ||
| Claims priority of application No. P2003-071942 (JP), filed on Mar. 17, 2003. | ||
| Prior Publication US 2004/0183159 A1, Sep. 23, 2004 | ||
| Int. Cl. H01L 29/00 (2006.01) | ||
| U.S. Cl. 257—526 [257/506; 257/565; 257/E29.171] | 18 Claims |
| 1. A semiconductor device comprising:
a) a semiconductor layer that is provided over an insulator layer that is provided over a support substrate layer, said insulator
layer having a lower thermal conductivity than the semiconductor layer;
b) a plurality of bipolar transistors that are provided on the semiconductor layer such that collectors, emitters and bases
of the bipolar transistors are respectively connected in parallel with each other; and
c) an isolation that is provided over a main surface of the semiconductor layer and that is constructed to have a depth that
does not reach through to the insulator layer and also does not reach the support substrate layer;
wherein one of a portion and a whole of the plurality of bipolar transistors are surrounded by the insulator layer, the isolation,
and an oxide film disposed within the isolation so as to not reach the support substrate layer, and
wherein the surrounded portion or whole of the plurality of transistors operates substantially uniformly as constituent elements
of a unit transistor.
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