US 7,575,994 B2
Semiconductor device and manufacturing method of the same
Yuichi Morita, Ora-gun (Japan); Shinzo Ishibe, Ora-Gun (Japan); Takashi Noma, Ota (Japan); Hisao Otsuka, Ora-Gun (Japan); Yukihiro Takao, Ota (Japan); and Hiroshi Kanamori, Tokyo (Japan)
Assigned to SANYO Electric Co., Ltd., Osaka (Japan)
Filed on Jun. 13, 2006, as Appl. No. 11/451,633.
Claims priority of application No. 2005-174922 (JP), filed on Jun. 15, 2005.
Prior Publication US 2007/0001302 A1, Jan. 04, 2007
Int. Cl. H01L 21/44 (2006.01)
U.S. Cl. 438—615  [257/737; 257/750; 257/766; 257/773; 257/E23.132; 438/614; 438/612; 438/613; 438/652; 438/666; 438/678] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate;
a pad electrode disposed on the substrate;
a first passivation film disposed on the substrate and having a first opening above the pad electrode so that an edge portion of the pad electrode is covered by the first passivation film;
a plating layer disposed on the pad electrode in the first opening;
a second passivation film disposed on the plating layer and the first passivation film and having a second opening above the plating layer, the second passivation film filling a gap between an edge portion of the plating layer and an edge portion of the first passivation film so as to contact the pad electrode; and
a conductive terminal disposed on the plating layer in the second opening,
wherein the first passivation film comprises an organic material,
the edge portion of the plating layer farthest from the conductive terminal is in direct contact with the pad electrode, and
the conductive terminal is disposed in the second opening of the second passivation film so that there is a separation in the second opening between the conductive terminal and the second passivation film.