| US 7,574,576 B2 | ||
| Semiconductor device and method of controlling the same | ||
| Kenta Kato, Aichi (Japan); Masahiko Okura, Aichi (Japan); Kenji Shibata, Aichi (Japan); Mitsuhiro Nagao, Aichi (Japan); and Stewart Wang, Fremont, Calif. (US) | ||
| Assigned to Spansion LLC, Sunnyvale, Calif. (US) | ||
| Filed on Dec. 22, 2006, as Appl. No. 11/644,161. | ||
| Prior Publication US 2008/0155217 A1, Jun. 26, 2008 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—163 | 10 Claims |
| 1. A semiconductor device comprising:
a memory cell array that includes non-volatile memory cells;
a first memory region and a second memory region that are located in the memory cell array, the first memory region being
protected during a protecting period, the second memory region being not protected;
an address change circuit that changes an address in an address space of the first memory region and the second memory region
in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and
a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting
period.
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