| US 7,574,554 B2 | ||
| Storage system and data protection method therefor | ||
| Katsuya Tanaka, Kokubunji (Japan); and Shuji Nakamura, Machida (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Aug. 11, 2006, as Appl. No. 11/503,050. | ||
| Prior Publication US 2008/0022163 A1, Jan. 24, 2008 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—103 | 15 Claims |
| 1. A storage system comprising:
one or more flash memory modules each comprising one or more flash memory chips and a memory controller operable to control
reading/writing of data from/to the flash memory chips; and
a storage controller comprising cache memory operable to temporarily store data read/written from/to one or more of the flash
memory chips,
wherein,
in the cache memory, data read/written from/to the flash memory chips is managed in units of first data lengths;
in the flash memory modules, the data read/written from/to the flash memory chips is managed in page units;
the memory area of one page includes a memory area of a second length from/to which the storage controller can read/write
data, and a memory area for a redundant section;
when writing data to a flash memory chip, the storage controller is operable to create a protection code enabling identification
of address information for a write destination page;
divide the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each
set composed of a piece of the divided write data and its protection code will be of the second data length, and write the
respective sets of the pieces of write data and protection codes in the flash memory chip in units of second data lengths;
and
the storage controller is operable to compare the address information identified with the protection codes attached to the
data read from the flash memory chip with the address information for the data that is intended to be read, and check whether
or not there is an address error.
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