| US 7,573,778 B2 | ||
| Semiconductor memory device | ||
| Shigeyuki Nakazawa, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Jul. 15, 2008, as Appl. No. 12/173,124. | ||
| Application 11/584899 is a division of application No. 10/455522, filed on Jun. 05, 2003, granted, now 6,974,194, filed on Dec. 19, 2006. | ||
| Application 12/173124 is a continuation of application No. 11/584899, filed on Oct. 23, 2006, granted, now 7,414,914. | ||
| Claims priority of application No. 2002-155854 (JP), filed on May 29, 2002. | ||
| Prior Publication US 2009/0021993 A1, Jan. 22, 2009 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—230.06 [365/230.08; 365/201; 365/233.1; 365/230.01] | 3 Claims |
| 1. A semiconductor memory device comprising:
a row address latch circuit for holding a row address input from an external source in synchronism with a timing signal having
a predetermined pulse duration;
a column address latch circuit for holding a column address input from an external source in synchronism with said timing
signal;
a first command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for
generating control signals corresponding to the commands, respectively;
a second command decoder responsive to a PACT command set for said test mode, for outputting a test control signal having
a predetermined pulse duration; and
a command selection circuit for outputting the test control signal output from said second command decoder to said row address
latch circuit, and stopping outputting the control signal output from said first command decoder to said row address latch
circuit, and holding a row address input together with said PACT command in said row address latch circuit when an active
command is input.
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