| US 7,568,177 B1 | ||
| System and method for power gating of an integrated circuit | ||
| Tobing Soebroto, Cupertino, Calif. (US); Ankur Gupta, Santa Clara, Calif. (US); Hendy Kosasih, Diamond Bar, Calif. (US); and Richard Chou, Cupertino, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Oct. 30, 2006, as Appl. No. 11/589,229. | ||
| Claims priority of provisional application 60/731239, filed on Oct. 31, 2005. | ||
| Int. Cl. G06F 17/50 (2006.01); G11C 5/14 (2006.01); H03K 17/16 (2006.01); H03K 19/094 (2006.01) | ||
| U.S. Cl. 716—9 [716/10; 716/13; 716/14; 326/33; 326/41; 326/47; 326/101; 326/80; 365/226] | 16 Claims |
| 1. An apparatus comprising:
a. an integrated circuit (IC) including a core and a plurality of individual input/output (I/O) pads surrounding the core;
and
b. a switching means formed in an integrated manner within at least one of the plurality of individual I/O pads for selectively
controlling transfer therethrough of a power supply signal to at least a portion of the core.
|