| US 7,568,174 B2 | ||
| Method for checking printability of a lithography target | ||
| Abdurrahman Sezginer, Monte Sereno, Calif. (US); and Bayram Yenikaya, San Jose, Calif. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Aug. 16, 2006, as Appl. No. 11/504,928. | ||
| Claims priority of provisional application 60/709881, filed on Aug. 19, 2005. | ||
| Prior Publication US 2007/0094634 A1, Apr. 26, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—4 [716/19; 716/21] | 33 Claims |
| 1. A computer implemented method of testing a target layout data set for a circuit design of an integrated circuit, wherein
the target layout data set represents a layer to be patterned onto a semiconductor wafer using a photolithographic imaging
process, the method comprising the steps of:
generating a first data set of a plurality of points at predetermined locations on a layer of the target layout;
generating a second data set of acceptable intensity thresholds at corresponding points on the layer of the target layout;
applying a plurality of sampling coefficients representing an optical property of the image to the first data set on the layer
to derive a range of intensities at the corresponding points; and
using a processor to compare intensities across the range of intensities at the predetermined points to the intensity thresholds
for those points to determine printability of the target layout.
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