| US 7,566,967 B2 | ||
| Semiconductor package structure for vertical mount and method | ||
| Stephen St. Germain, Scottsdale, Ariz. (US); Francis J. Carney, Queen Creek, Ariz. (US); and Bruce Alan Huing, Buckeye, Ariz. (US) | ||
| Assigned to Semiconductor Components Industries, L.L.C., Phoenix, Ariz. (US) | ||
| Filed on Jan. 22, 2008, as Appl. No. 12/17,856. | ||
| Prior Publication US 2008/0111227 A1, May 15, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 23/538 (2006.01) | ||
| U.S. Cl. 257—727 [257/177; 257/686; 257/777; 257/E23.178] | 20 Claims |
| 1. A semiconductor package structure comprising:
first and second clips each having an end configured for mounting the semiconductor package structure in a perpendicular orientation
with respect to a next level of assembly, and wherein the second clip is configured as a control electrode;
a semiconductor chip interposed between the first and second clips, the first clip coupled to one major surface of the semiconductor
chip, and the second clip coupled to another major surface of the semiconductor chip;
a third clip interposed between the first and second clips and coupled to one of the major surfaces of the semiconductor chip,
wherein the third upright clip has an end configured for mounting the semiconductor package in a perpendicular orientation
with respect to the next level of assembly;
a first spacer interposed between the first and third clips; and
a second spacer interposed between the second and third upright clips.
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