| US 7,565,513 B2 | ||
| Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations | ||
| Ashraf Ahmed, Austin, Tex. (US); Kelvin Domnic Goveas, Austin, Tex. (US); Michael Clark, Austin, Tex. (US); and Jelena Ilic, Austin, Tex. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Feb. 28, 2007, as Appl. No. 11/680,331. | ||
| Prior Publication US 2008/0209184 A1, Aug. 28, 2008 | ||
| Int. Cl. G06F 9/302 (2006.01) | ||
| U.S. Cl. 712—222 [712/209; 713/324] | 20 Claims |
| 1. A method, comprising:
determining whether a floating point unit (FPU) of a processor is to operate in full-bit mode or a reduced-bit mode;
fetching an instruction;
in response to determining the FPU is to operate in the full-bit mode, decoding the instruction into a single operation; and
in response to determining the FPU is to operate in the reduced-bit mode, decoding the instruction into multiple operations.
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