| US 7,564,737 B2 | ||
| Memory data transfer | ||
| Joseph D. Macri, San Francisco, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Aug. 30, 2007, as Appl. No. 11/847,749. | ||
| Claims priority of provisional application 60/841389, filed on Aug. 30, 2006. | ||
| Prior Publication US 2008/0080298 A1, Apr. 03, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—233 [365/194] | 17 Claims |
| 1. A method for controlling data output by a memory device, the method comprising:
receiving, at a clock generator coupled to a controller, a first clock signal having a first frequency;
producing, at the clock generator, a second and third clock signals from the first clock signal, the second and third clock
signals having second and third frequencies, respectively, that are substantially equal to the first frequency, the second
and third clock signals being out of phase relative to each other; and
outputting, at the controller, a first data in response to a rising edge of the second clock signal and a second data in response
to another rising edge of the third clock signal.
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