| US 7,563,731 B2 | ||
| Field effect transistor having a stressed dielectric layer based on an enhanced device topography | ||
| Christoph Schwan, Gebhardshain (Germany); Manfred Horstmann, Duerrrhoehrsdorf-Dittersbach (Germany); Kai Frohberg, Niederau (Germany); and Rolf Stephan, Dresden (Germany) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on Apr. 24, 2007, as Appl. No. 11/739,279. | ||
| Claims priority of application No. 10 2006 046 375 (DE), filed on Sep. 29, 2006. | ||
| Prior Publication US 2008/0081486 A1, Apr. 03, 2008 | ||
| Int. Cl. H01L 21/31 (2006.01); H01L 21/469 (2006.01) | ||
| U.S. Cl. 438—792 [438/902; 257/E21.478; 257/E21.64; 257/638; 257/E29.132] | 21 Claims |
| 1. A method, comprising:
forming a first dielectric layer above a transistor having a gate electrode, said first dielectric layer having a predefined
type of intrinsic stress;
planarizing said first dielectric layer;
forming a first placeholder structure above said gate electrode after planarizing said first dielectric layer to locally increase
a device height above said gate electrode; and
forming a second dielectric layer above said transistor and said first placeholder structure, said second dielectric layer
having said predefined type of intrinsic stress.
|