| US 7,563,723 B2 | ||
| Critical dimension control for integrated circuits | ||
| Mirzafer K. Abatchev, Boise, Id. (US); David K. Hwang, Boise, Id. (US); and Robert G. Veltrop, Eagle, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Aug. 03, 2006, as Appl. No. 11/498,707. | ||
| Application 11/498707 is a continuation of application No. 10/931772, filed on Aug. 31, 2004, granted, now 7,271,106. | ||
| Prior Publication US 2006/0270230 A1, Nov. 30, 2006 | ||
| Int. Cl. H01L 21/302 (2006.01) | ||
| U.S. Cl. 438—714 [438/706; 430/313] | 18 Claims |
| 1. A method for altering a critical dimension in an integrated circuit comprising:
patterning a photoresist layer to form a plurality of resist elements;
shrinking at least some of the resist elements to provide shrunken resist elements;
etching a first hard mask layer to form a pattern corresponding to the shrunken resist elements to form a plurality of physical
elements of the first hard mask layer; and
transferring the pattern from the first hard mask layer into a substantially carbon layer using an etchant comprising sulfur
and oxygen.
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