an initial synchronizing unit for outputting a first output enable signal when a read CAS signal is activated;

a plurality of stages of additional synchronizing units, connected in series, each for outputting an output signal of a previous stage as an output enable signal in synchronization with a corresponding driving clock, a first of the stages receiving the first output enable signal; and

a test unit for adjusting a delay amount of an input clock according to a plurality of test signals and outputting the driving clock,

wherein the test unit includes a plurality of delay adjusting units which increase or decrease the delay amount of the input clock according to a test-delay increment signal, a test-delay decrement signal, and a test-delay normal signal, and output driving clocks.