| US 7,548,485 B2 | ||
| Semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof | ||
| Young-Seung Kim, Seodaemun-gu (Korea, Republic of); and Chul-Sung Park, Seocho-gu (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Aug. 27, 2007, as Appl. No. 11/845,191. | ||
| Claims priority of application No. 10-2007-0001970 (KR), filed on Jan. 08, 2007. | ||
| Prior Publication US 2008/0165610 A1, Jul. 10, 2008 | ||
| Int. Cl. G11C 8/02 (2006.01) | ||
| U.S. Cl. 365—233.1 [365/189.08; 365/233.19] | 18 Claims |
| 1. A semiconductor memory device that operates in a first mode and a second mode, the semiconductor memory device comprising:
a memory cell array comprising a plurality of memory cells arrayed in columns and rows in a matrix;
a peripheral circuit coupled to the memory cell array and configured to write data to the memory cell array and to read data
from the memory cell array; and
a bypass control unit coupled to the peripheral unit, the bypass control unit configured to enable a late write operation
and a bypass operation of the peripheral circuit when the semiconductor memory device operates in the first mode and to disable
the late write operation and the bypass operation of the peripheral circuit when the semiconductor memory device operates
in the second mode.
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