| US 7,548,235 B2 | ||
| Data processing apparatus | ||
| Mitsuaki Oshima, Kyoto (Japan); Yoshihiro Gohara, Toyono-gun (Japan); Yoshinori Kobayashi, Hirakata (Japan); Shozo Fujiwara, Ibaraki (Japan); and Tsuyoshi Uemura, Kadoma (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jan. 31, 2005, as Appl. No. 11/45,393. | ||
| Application 11/045393 is a division of application No. 10/772352, filed on Feb. 06, 2004, granted, now 6,952,787. | ||
| Application 10/772352 is a division of application No. 10/194687, filed on Jul. 24, 2002, granted, now 6,804,791. | ||
| Application 10/194687 is a division of application No. 09/583168, filed on May 30, 2000, granted, now 6,535,985, filed on Mar. 18, 2003. | ||
| Application 09/583168 is a continuation of application No. 08/283165, filed on Aug. 03, 1994, abandoned. | ||
| Application 08/283165 is a continuation of application No. 07/671929, filed on Mar. 20, 1991, abandoned. | ||
| Claims priority of application No. 2-73737 (JP), filed on Mar. 23, 1990. | ||
| Prior Publication US 2005/0128179 A1, Jun. 16, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G09G 5/00 (2006.01); G06F 1/00 (2006.01) | ||
| U.S. Cl. 345—211 [345/97; 345/102; 345/168; 713/322; 713/323; 713/324; 713/330] | 18 Claims |
| 1. A computer comprising:
an information inputting section operable to input information external to the computer;
a first processing section;
a second processing section operable to perform a predetermined process; and
a display section operable to display a result of the predetermined process performed by the second processing section,
wherein:
the first processing section is operable to operate in accordance with a first clock having a first frequency,
the second processing section has an operation state, a stop state and a power supply stop state, in the operation state the
second processing section operates in accordance with a second clock having a second frequency which is higher than the first
frequency, in the stop state the second processing section stops operating in accordance with the second clock while the power
supply to the second processing section is maintained, in the power supply stop state the power supply to the second processing
section is stopped,
the first processing section is operable, when the second processing section is in the stop state, to process the information
inputted by the information inputting section, to determine whether it is necessary to initiate the second processing section
and provide to the second processing section, if necessary, an output for initiating the second processing section and at
least part of the information inputted by the information inputting section,
the second processing section in the stop state is operable to make a transition from the stop state to the operation state
based on the output for initiating the second processing section output from the first processing section,
the second processing section in the power supply stop state is operable to make a transition from the power supply stop state
to one of the stop state and the operation state based on an output from the first processing section, and
the second processing section in the operation state is operable to perform the predetermined process based on the at least
part of the information output from the first processing section.
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